pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention in the access to the NoC among running tasks. Probabilistic Timing Analysis (PTA) is a powerful approach to derive WCET estimates on relatively complex processors. However, so far it has only been tested on small multicores comprising an on-chip bus as communication means, which intrinsically does not scale to high core counts. In this paper we propose pTNoC, a new tree-based NoC design compatible with PTA requirements and delivering scalability towards medium/large core counts. pTNoC provides tight WCET estimates by means of asymmetric bandwidth guarantees for mixed-criticality systems with negligible impact on average performance. Finally, our implementation results show the reduced area and power costs of the pTNoC.
CitacióSlijepcevic, M., Fernández, M., Hernández, C., Abella, J., Quiñones, E., Cazorla, F. pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems. A: Euromicro Conference on Digital Systems Design. "19th Euromicro Conference on Digital System Design, DSD 2016: 31 August-2 September 2016 Limassol, Cyprus: proceedings". Limasol: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 404-412.
Versió de l'editorhttp://ieeexplore.ieee.org/abstract/document/7723580/