dc.contributor.author | Vourkas, Ioanis |
dc.contributor.author | Abusleme, A. |
dc.contributor.author | Ntinas, V. |
dc.contributor.author | Sirakoulis, Georgios Ch. |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2016-11-24T13:58:47Z |
dc.date.issued | 2016 |
dc.identifier.citation | Vourkas, I., Abusleme, A., Ntinas, V., Sirakoulis, G., Rubio, A. A digital memristor emulator for FPGA-based artificial neural networks. A: IEEE International Verification and Security Workshop. "2016 1st IEEE International Verification and Security Workshop (IVSW 2016): Sant Feliu de Guixols, Spain: 4-6 July 2016". Sant Feliu de Guixols, Girona: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 54-57. |
dc.identifier.isbn | 978-1-5090-1141-4 |
dc.identifier.uri | http://hdl.handle.net/2117/97184 |
dc.description.abstract | FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain human brain-like functionalities at circuit-level. In this context, the memristor has been proposed as the electronic
analogue of biological synapses, but the price of commercially available samples still remains high, hence motivating the development of HW emulators. In this work we present the first digital memristor emulator based upon a voltagecontrolled threshold-type bipolar memristor model. We validate its functionality in low-cost yet powerful FPGA families. We test its suitability for complex memristive circuits and prove its synaptic properties in a small associative memory
via a perceptron ANN. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica |
dc.subject.lcsh | Neural networks (Computer science) |
dc.subject.lcsh | Computer security |
dc.subject.other | Circuit testing |
dc.subject.other | Digital circuits |
dc.subject.other | Field programmable gate arrays |
dc.subject.other | Memristor circuits |
dc.subject.other | Neural nets |
dc.subject.other | Perceptron ANN |
dc.subject.other | Memristive circuits |
dc.subject.other | Voltage-controlled threshold-type bipolar memristor model |
dc.subject.other | FPGA-based artificial neural networks |
dc.subject.other | Digital memristor emulator |
dc.title | A digital memristor emulator for FPGA-based artificial neural networks |
dc.type | Conference report |
dc.subject.lemac | Xarxes neuronals (Informàtica) |
dc.subject.lemac | Seguretat informàtica |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/IVSW.2016.7566607 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/7566607/ |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 19074367 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Vourkas, I.; Abusleme, A.; Ntinas, V.; Sirakoulis, G.; Rubio, A. |
local.citation.contributor | IEEE International Verification and Security Workshop |
local.citation.pubplace | Sant Feliu de Guixols, Girona |
local.citation.publicationName | 2016 1st IEEE International Verification and Security Workshop (IVSW 2016): Sant Feliu de Guixols, Spain: 4-6 July 2016 |
local.citation.startingPage | 54 |
local.citation.endingPage | 57 |