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dc.contributor.authorJalle Ibarra, Javier
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorFossati, Luca
dc.contributor.authorZulianello, Marco
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationJalle, J., Quiñones, E., Abella, J., Fossati, L., Zulianello, M., Cazorla, F. Data bus slicing for contention-free multicore real-time memory systems. A: IEEE International Symposium on Industrial Embedded Systems. "2016 11th IEEE International Symposium on Industrial Embedded Systems (SIES): Krakow, Poland 23-25 May 2016: proceedings". Krakow: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-8.
dc.description.abstractMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well with increasing complexity of multicores, leading to a rapid increase of WCET estimates. This is due to fact that requests from different tasks interleave in the access to memory, and for each of its requests a task has to make worstcase time allowances to account for the memory state left by the previous request, that may belong to a different task. In this paper, we propose a memory organization that controls contention by dividing the data bus into narrower independent data buses, thus removing conflicts among different tasks accessing memory. While narrower data buses require extra transfers, they allow exploiting memory locality, hence only slightly affecting average performance. Our evaluation on a solid space case-study shows that the proposed memory organization provides contention-free memory access facilitating timing analysis and tightening WCET estimates.
dc.description.sponsorshipThe research leading to these results has received funding from the European Space Agency under contract NPI 4000102880 and the Ministry of Science and Technology of Spain under contract TIN-2015-65316-P. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.
dc.format.extent8 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshReal-time data processing
dc.subject.lcshMultiprocessors -- Programming
dc.subject.otherEmbedded systems
dc.subject.otherMemory architecture
dc.subject.otherSystem buses
dc.subject.otherControl memory
dc.subject.otherMemory access
dc.subject.otherMemory locality
dc.subject.otherMemory organizations
dc.subject.otherMemory systems
dc.subject.otherTime variability
dc.subject.otherTiming Analysis
dc.titleData bus slicing for contention-free multicore real-time memory systems
dc.typeConference report
dc.subject.lemacTemps real (Informàtica)
dc.subject.lemacMultiprocessadors -- Programació
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
local.citation.authorJalle, J.; Quiñones, E.; Abella, J.; Fossati, L.; Zulianello, M.; Cazorla, F.
local.citation.contributorIEEE International Symposium on Industrial Embedded Systems
local.citation.publicationName2016 11th IEEE International Symposium on Industrial Embedded Systems (SIES): Krakow, Poland 23-25 May 2016: proceedings

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