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dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorParcerisa Bundó, Joan Manuel
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationQuiñones, E., Parcerisa, Joan-Manuel, González, A. Improving branch prediction and predicated execution in out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2007 IEEE 13th International Symposium on High Performance Computer Architecture". Phoenix, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 75-84.
dc.description.abstractIf-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a negative side-effect because the removal of branches eliminates useful correlation information necessary for conventional branch predictors. The remaining branches may become harder to predict. However, in predicated ISAs with a compare-branch model, the correlation information not only resides in branches, but also in compare instructions that compute their guarding predicates. When a branch is removed, its correlation information is still available in its compare instruction. We propose a branch prediction scheme based on predicate prediction. It has three advantages: First, since the prediction is not done on a branch basis but on a predicate define basis, branch removal after if-conversion does not lose any correlation information, so accuracy is not degraded. Second, the mechanism we propose permits using the computed value of the branch predicate when available, instead of the predicted value, thus effectively achieving 100% accuracy on such early-resolved branches. Third, as shown in previous work, the selective predicate prediction is a very effective technique to implement if-conversion on out-of-order processors, since it avoids the problem of multiple register definitions and reduces the unnecessary resource consumption of nullified instructions. Hence, our approach enables a very efficient implementation of if-conversion for an out-of-order processor, with almost no additional hardware cost, because the same hardware is used to predict the predicates of if-converted code and to predict branches without accuracy degradation.
dc.format.extent10 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.otherOut of order
dc.subject.otherInstruction sets
dc.subject.otherComputer aided instruction
dc.titleImproving branch prediction and predicated execution in out-of-order processors
dc.typeConference report
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
upcommons.citation.authorQuiñones, E., Parcerisa, Joan-Manuel, González, A.
upcommons.citation.contributorInternational Symposium on High-Performance Computer Architecture
upcommons.citation.pubplacePhoenix, AZ
upcommons.citation.publicationName2007 IEEE 13th International Symposium on High Performance Computer Architecture

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