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dc.contributor.authorLlosa Espuny, José Francisco
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2016-11-17T14:02:49Z
dc.date.available2016-11-17T14:02:49Z
dc.date.issued1995
dc.identifier.citationLlosa, J., Valero, M., Ayguadé, E., González, A. Hypernode reduction modulo scheduling. A: Annual IEEE/ACM International Symposium on Microarchitecture. "Proceedings of the 28th Annual International Symposium on Microarchitecture: November 29-December 1,1995, Ann Arbor, Michigan". Michigan: Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 350-360.
dc.identifier.isbn0-8186-7349-4
dc.identifier.urihttp://hdl.handle.net/2117/96797
dc.description.abstractSoftware pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution time, without regarding register requirements. Most strategies tend to stretch operand lifetimes because they schedule some operations too early or too late. The paper presents a novel strategy that simultaneously schedules some operations late and other operations early, minimizing all the stretchable dependencies and therefore reducing the registers required by the loop. The key of this strategy is a pre-ordering that selects the order in which the operations will be scheduled. The results show that the method described in this paper performs better than other heuristic methods and almost as well as a linear programming method but requiring much less time to produce the schedules.
dc.format.extent11 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshLinear programming
dc.subject.otherInstruction scheduling
dc.subject.otherLoop scheduling
dc.subject.otherSoftware pipelining
dc.subject.otherRegister allocation
dc.subject.otherRegister spilling
dc.titleHypernode reduction modulo scheduling
dc.typeConference report
dc.subject.lemacProgramació lineal
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/MICRO.1995.476844
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/476844/
dc.rights.accessOpen Access
drac.iddocument2363211
dc.description.versionPostprint (published version)
upcommons.citation.authorLlosa, J.; Valero, M.; Ayguadé, E.; González, A.
upcommons.citation.contributorAnnual IEEE/ACM International Symposium on Microarchitecture
upcommons.citation.pubplaceMichigan
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 28th Annual International Symposium on Microarchitecture: November 29-December 1,1995, Ann Arbor, Michigan
upcommons.citation.startingPage350
upcommons.citation.endingPage360


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