Hardware schemes for early register release
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the size and number of ports of the register file. In conventional register renaming schemes, register releasing is conservatively done only after the instruction that redefines the same register is committed. Instead, we propose a scheme that releases registers as soon as the processor knows that there will be no further use of them. We present two early releasing hardware implementations with different performance/complexity trade-offs. Detailed cycle-level simulations show either a significant speedup for a given register file size, or a reduction in register file size for a given performance level.
CitationMonreal, T., Viñals, V., González, A., Valero, M. Hardware schemes for early register release. A: International Conference on Parallel Processing. "International Conference on Parallel Processing: 18-21 August 2002 Vancouver, B.C., Canada: proceedings". Vancouver: Institute of Electrical and Electronics Engineers (IEEE), 2002, p. 5-13.