Graph-partitioning based instruction scheduling for clustered processors
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
This paper presents a novel scheme to schedule loops for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques followed by a scheduling phase that integrates register allocation and spill code generation. The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated. Results show a significant speedup when compared with previously proposed techniques. For some processor configuration the average speedup for the SPECfp95 is 23% with respect to the published scheme with the best performance. Besides, the proposed scheme is much faster (between 2-7 times, depending on the configuration).
CitationAleta, A., Codina, J.M., Sanchez, F., Gonzalez, A. Graph-partitioning based instruction scheduling for clustered processors. A: Annual IEEE/ACM International Symposium on Microarchitecture. "34th ACM/IEEE International Symposium on Microarchitecture, 2001, MICRO-34: proceedings". Austin: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 150-159.
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