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dc.contributor.authorChronaki, Kallia
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorCasas Guix, Marc
dc.contributor.authorRico, Alejandro
dc.contributor.authorBadia Sala, Rosa Maria
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2016-11-15T09:19:43Z
dc.date.available2016-11-15T09:19:43Z
dc.date.issued2016
dc.identifier.citationChronaki, K., Moreto, M., Casas, M., Rico, A., Badia, R.M., Ayguadé, E., Labarta, J., Valero, M. POSTER: Exploiting asymmetric multi-core processors with flexible system sofware. A: International Conference on Parallel Architectures and Compilation Techniques. "PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation". Haifa: Association for Computing Machinery (ACM), 2016, p. 415-417.
dc.identifier.isbn978-1-4503-4121-9
dc.identifier.urihttp://hdl.handle.net/2117/96641
dc.description.abstractEnergy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while keeping high performance. However, it is not known yet whether such systems are ready to handle parallel applications. This paper fills this gap by evaluating emerging parallel applications on an asymmetric multi-core. We make use of the PARSEC benchmark suite and a processor that implements the ARM big.LITTLE architecture. We conclude that these applications are not mature enough to run on such systems, as they suffer from load imbalance. Furthermore, we explore the behaviour of dynamic scheduling solutions on either the Operating System (OS) or the runtime level. Comparing these approaches shows us that the most efficient scheduling takes place in the runtime level, influencing the future research towards such solutions.
dc.description.sponsorshipThis work has been supported by the Spanish Government (SEV2015-0493), by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), by the RoMoL ERC Advanced Grant (GA 321253) and the European HiPEAC Network of Excellence. The Mont-Blanc project receives funding from the EU's Seventh Framework Programme (FP7/2007-2013) under grant agreement number 610402 and from the EU's H2020 Framework Programme (H2020/2014-2020) under grant agreement number 671697. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047. M. Casas is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP B 00243).
dc.format.extent3 p.
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshHigh performance computing -- Energy conservation
dc.subject.otherEnergy conservation
dc.subject.otherEnergy efficiency
dc.subject.otherMemory architecture
dc.subject.otherParallel architectures
dc.subject.otherParallel processing systems
dc.subject.otherScheduling
dc.subject.otherCache coherence
dc.subject.otherDynamic scheduling
dc.subject.otherEfficient scheduling
dc.subject.otherHigh performance computin (HPC)
dc.subject.otherMemory consistency
dc.subject.otherMulti-core processor
dc.subject.otherMulticore architectures
dc.subject.otherParallel application
dc.titlePOSTER: Exploiting asymmetric multi-core processors with flexible system sofware
dc.typeConference lecture
dc.subject.lemacCàlcul intensiu (Informàtica) -- Estalvi d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/2967938.2976038
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?doid=2967938.2976038
dc.rights.accessOpen Access
local.identifier.drac19160745
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/610402/EU/Mont-Blanc 2, European scalable and power efficient HPC platform based onlow-power embedded technology/MONT-BLANC 2
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology/Mont-Blanc 3
local.citation.authorChronaki, K.; Moreto, M.; Casas, M.; Rico, A.; Badia, R.M.; Ayguadé, E.; Labarta, J.; Valero, M.
local.citation.contributorInternational Conference on Parallel Architectures and Compilation Techniques
local.citation.pubplaceHaifa
local.citation.publicationNamePACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation
local.citation.startingPage415
local.citation.endingPage417


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