POSTER: Exploiting asymmetric multi-core processors with flexible system sofware
Tipo de documentoComunicación de congreso
Fecha de publicación2016
EditorAssociation for Computing Machinery (ACM)
Condiciones de accesoAcceso abierto
Proyecto de la Comisión EuropeaMONT-BLANC 2 - Mont-Blanc 2, European scalable and power efficient HPC platform based onlow-power embedded technology (EC-FP7-610402)
ROMOL - Riding on Moore's Law (EC-FP7-321253)
Mont-Blanc 3 - Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology (EC-H2020-671697)
Energy efficiency has become the main challenge for high performance computing (HPC). The use of mobile asymmetric multi-core architectures to build future multi-core systems is an approach towards energy savings while keeping high performance. However, it is not known yet whether such systems are ready to handle parallel applications. This paper fills this gap by evaluating emerging parallel applications on an asymmetric multi-core. We make use of the PARSEC benchmark suite and a processor that implements the ARM big.LITTLE architecture. We conclude that these applications are not mature enough to run on such systems, as they suffer from load imbalance. Furthermore, we explore the behaviour of dynamic scheduling solutions on either the Operating System (OS) or the runtime level. Comparing these approaches shows us that the most efficient scheduling takes place in the runtime level, influencing the future research towards such solutions.
CitaciónChronaki, K., Moreto, M., Casas, M., Rico, A., Badia, R.M., Ayguadé, E., Labarta, J., Valero, M. POSTER: Exploiting asymmetric multi-core processors with flexible system sofware. A: International Conference on Parallel Architectures and Compilation Techniques. "PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation". Haifa: Association for Computing Machinery (ACM), 2016, p. 415-417.
Versión del editorhttp://dl.acm.org/citation.cfm?doid=2967938.2976038