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Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/
| dc.contributor.author | Grigorios, Magklis |
| dc.contributor.author | González González, José |
| dc.contributor.author | González Colás, Antonio María |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2016-11-11T12:44:40Z |
| dc.date.available | 2016-11-11T12:44:40Z |
| dc.date.issued | 2004 |
| dc.identifier.citation | Grigorios, M., González, J., González, A. Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/. A: IEEE International Conference on Computer Design: VLSI in Computers and Processors. "IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004, ICCD 2004: proceedings". San Jose, CA: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 250-255. |
| dc.identifier.isbn | 0-7695-2231-9 |
| dc.identifier.uri | http://hdl.handle.net/2117/96553 |
| dc.description.abstract | In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay/sup 2/ product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound). |
| dc.format.extent | 6 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Microprocessors |
| dc.subject.other | Frequency |
| dc.subject.other | Clocks |
| dc.subject.other | Power dissipation |
| dc.subject.other | Microarchitecture |
| dc.subject.other | Dynamic voltage scaling |
| dc.subject.other | Wire |
| dc.subject.other | Delay |
| dc.subject.other | Control systems |
| dc.title | Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/ |
| dc.type | Conference report |
| dc.subject.lemac | Microprocessadors |
| dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
| dc.identifier.doi | 10.1109/ICCD.2004.1347930 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1347930/ |
| dc.rights.access | Open Access |
| local.identifier.drac | 2358499 |
| dc.description.version | Postprint (published version) |
| local.citation.author | Grigorios, M.; González, J.; González, A. |
| local.citation.contributor | IEEE International Conference on Computer Design: VLSI in Computers and Processors |
| local.citation.pubplace | San Jose, CA |
| local.citation.publicationName | IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004, ICCD 2004: proceedings |
| local.citation.startingPage | 250 |
| local.citation.endingPage | 255 |
