Ring oscillator clocks and margins

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Document typeConference report
Defense date2016
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Abstract
How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.
CitationCortadella, J., Lupon, M., Moreno, A., Roca, A., Sapatnekar, S. Ring oscillator clocks and margins. A: IEEE International Symposium on Asynchronous Circuits and Systems. "22nd IEEE International Symposium on Asynchronous Circuits and Systems: 8-11 May 2016 Porto Alegre, Brazil: proceedings". Porto Alegre: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 19-26.
ISBN978-1-4673-9007-1
Publisher versionhttp://ieeexplore.ieee.org/document/7584887/
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