Ring oscillator clocks and margins
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.
CitacióCortadella, J., Lupon, M., Moreno, A., Roca, A., Sapatnekar, S. Ring oscillator clocks and margins. A: IEEE International Symposium on Asynchronous Circuits and Systems. "22nd IEEE International Symposium on Asynchronous Circuits and Systems: 8-11 May 2016 Porto Alegre, Brazil: proceedings". Porto Alegre: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 19-26.
Versió de l'editorhttp://ieeexplore.ieee.org/document/7584887/