CVD graphene-FET based cascode circuits: a design exploration and fabrication towards intrinsic gain enhancement
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
This paper presents the design exploration of a basic cascode circuit (CAS) targeted to increase the intrinsic gain A# of a graphene field-effect-transistor (GFET) by decreasing its output conductance go. First, the parameters of a large-signal compact-model, based on drift-diffusion carrier transport, are fit to measurements carried on 2 CVD GFETs, fabricated independently by different research groups. Second, CAS circuits are simulated to perform a design exploration and provide design guidelines. Third, CAS circuits are fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance gm and hence A#. Against these metrics, a quantitative comparison between CAS and GFET is performed and conclusions are derived.
CitationIannazzo, M., Alarcon, E., Pandey, H., Passi, V., Lemme, M. CVD graphene-FET based cascode circuits: a design exploration and fabrication towards intrinsic gain enhancement. A: European Solid-State Device Research Conference. "2016 46th European Solid-State Device Research Conference (ESSDERC): Lausanne, Switzerland: 12-15 September 2016". Lausanne: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 244-247.
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