Cache designs for reliable hybrid high and ultra-low voltage operation
Visualitza/Obre
10.5821/dissertation-2117-95289
Inclou dades d'ús des de 2022
Cita com:
hdl:2117/95289
Càtedra / Departament / Institut
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Tipus de documentTesi
Data de defensa2014-05-16
EditorUniversitat Politècnica de Catalunya
Condicions d'accésAccés obert
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continguts d'aquesta obra estan subjectes a la llicència de Creative Commons
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Reconeixement-NoComercial 3.0 Espanya
Abstract
Increasing demand for implementing highly-miniaturized battery-powered ultra-low-cost systems (e.g., below 1 USD) in emerging applications such as body, urban life and environment monitoring, etc., has introduced many challenges in the chip design. Such applications require high performance occasionally, but very little energy consumption during most of the time in order to extend battery lifetime. In addition, they require real-time guarantees. The most suitable technological solution for those devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/sub-threshold (NST) voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and it is mandatory trading off different SRAM designs, especially in cache memories, which occupy most of the processor¿s area.
In this Thesis, we analyze the performance/power tradeoffs involved in the design of SRAM L1 caches for reliable hybrid high and NST Vcc operation from a microarchitectural perspective. We develop new, simple, single-Vcc domain hybrid cache architectures and data management mechanisms that satisfy all stringent needs of our target market. Proposed solutions are shown to have high energy efficiency with negligible impact on average performance while maintaining strong performance guarantees as required for our target market.
CitacióMaric, B. Cache designs for reliable hybrid high and ultra-low voltage operation. Tesi doctoral, UPC, Departament d'Arquitectura de Computadors, 2014. DOI 10.5821/dissertation-2117-95289. Disponible a: <http://hdl.handle.net/2117/95289>
Dipòsit legalB 16009-2014
Col·leccions
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TBM1de1.pdf | 4,514Mb | Visualitza/Obre |