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dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorManich Bou, Salvador
dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-11-02T13:56:52Z
dc.date.issued2016
dc.identifier.citationArumi, D., Manich, S., Rodriguez, R. RRAM based cell for hardware security applications. A: International Verification and Security Workshop. "Proceedings of the 2016 1st IEEE International Verification and Security Workshop (IVSW)". St. Feliu de Guixols: 2016, p. 7-12.
dc.identifier.isbn978-1-5090-1141-4
dc.identifier.urihttp://hdl.handle.net/2117/91350
dc.description.abstractResistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs will poses challenges that must be overcome prior to their massive memory commercialization. However, these very same features open a wide range of potential applications for these devices in hardware security. In this context, this work proposes the generation of a random bit by means of simultaneous write opeation of two paralled cells so that only one of them unpredictably switches its state. Electrical simulations confirm the strong stochastic behavior and stability of the proposed primitive. Exploiting this fact, a Physical Unclonable Function (PUF)like primitive is implemented based on modified 1 transistor - 1 resistor (1T1R) array structure.
dc.format.extent6 p.
dc.language.isoeng
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshRandom access memory
dc.subject.lcshStochastic systems
dc.subject.lcshComputer security
dc.subject.otherrandom-access storage
dc.subject.othersecurity of data
dc.subject.otherstochastic processes
dc.subject.otherRRAM based cell
dc.subject.otherhardware security applications
dc.subject.otherresistive random access memories
dc.subject.otherRRAMs
dc.subject.othernonvolatile memories
dc.subject.otherstochastic switching mechanism
dc.subject.otherintrinsic variability
dc.subject.othermemory commercialization
dc.subject.otherrandom bit generation
dc.subject.otherparalled cells
dc.subject.otherelectrical simulations
dc.subject.otherstochastic behavior
dc.subject.otherphysical unclonable function like primitive
dc.subject.otherPUF like primitive
dc.subject.othermodified 1 transistor-1 resistor array structure
dc.subject.other1T1R array structure
dc.titleRRAM based cell for hardware security applications
dc.typeConference report
dc.subject.lemacOrdinadors--Dispositius de memòria
dc.subject.lemacProcessos estocàstics -- Informàtica
dc.subject.lemacSeguretat informàtica
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.doi10.1109/IVSW.2016.7566599
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
drac.iddocument19074686
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorArumi, D.; Manich, S.; Rodriguez, R.
upcommons.citation.contributorInternational Verification and Security Workshop
upcommons.citation.pubplaceSt. Feliu de Guixols
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 2016 1st IEEE International Verification and Security Workshop (IVSW)
upcommons.citation.startingPage7
upcommons.citation.endingPage12


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