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dc.contributor.authorSubasi, Omer
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.authorYalcin, Gulay
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationSubasi, O., Unsal, O., Labarta, J., Yalcin, G., Cristal, A. CRC-based memory reliability for task-parallel HPC applications. A: IEEE International Symposium on Parallel and Distributed Processing. "2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016): Chicago, Illinois, USA: 23-27 May 2016". Chicago, Illinois: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1101-1112.
dc.description.abstractMemory reliability will be one of the major concerns for future HPC and Exascale systems. This concern is mostly attributed to the expected massive increase in memory capacity and the number of memory devices in Exascale systems. For memory systems Error Correcting Codes (ECC) are the mostcommonly used mechanism. However state-of-the art hardware ECCs will not be sufficient in terms of error coverage for future computing systems and stronger hardware ECCs providing more coverage have prohibitive costs in terms of area, power and latency. Software-based solutions are needed to cooperate with hardware. In this work, we propose a Cyclic Redundancy Checks (CRCs) based software mechanism for task-parallel HPC applications. Our mechanism incurs only 1.7% performance overheadwith hardware acceleration while being highly scalable at large scale. Our mathematical analysis demonstrates the effectiveness of our scheme and its error coverage. Results show that our CRC-based mechanism reduces the memory vulnerability by 87% on average with up to 32-bit burst (consecutive) and 5-bit arbitrary error correction capability.
dc.description.sponsorshipThis work was supported by FI-DGR 2013 scholarship and the European Community’s Seventh Framework Programme [FP7/2007-2013] under the Mont-blanc 2 Project (, grant agreement no. 610402 and TIN2015-65316-P.
dc.format.extent12 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherApplication programs
dc.subject.otherData flow analysis
dc.subject.otherError correction
dc.subject.otherReconfigurable hardware
dc.subject.otherCyclic redundancy check
dc.subject.otherDataflow model
dc.subject.otherError correction capability
dc.subject.otherHardware acceleration
dc.subject.otherMathematical analysis
dc.subject.otherMemory reliability
dc.subject.otherSoftware-based solutions
dc.subject.otherTask parallelism
dc.titleCRC-based memory reliability for task-parallel HPC applications
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
local.citation.authorSubasi, O.; Unsal, O.; Labarta, J.; Yalcin, G.; Cristal, A.
local.citation.contributorIEEE International Symposium on Parallel and Distributed Processing
local.citation.pubplaceChicago, Illinois
local.citation.publicationName2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2016): Chicago, Illinois, USA: 23-27 May 2016

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