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AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures
dc.contributor.author | Aleta Ortega, Alexandre |
dc.contributor.author | Codina Viñas, Josep M. |
dc.contributor.author | Sánchez Navarro, F. Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Kaeli, D |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2016-10-27T07:26:29Z |
dc.date.available | 2016-10-27T07:26:29Z |
dc.date.issued | 2009-06 |
dc.identifier.citation | Aleta, A., Codina, J.M., Sánchez, F., González, A., Kaeli, D. AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures. "IEEE transactions on computers", Juny 2009, vol. 58, núm. 6, p. 770-783. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/91144 |
dc.description.abstract | This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the number of intercluster communications at the same time. Partitioning is guided by approximate schedules (i.e., pseudoschedules), which take into account all of the constraints that influence the final schedule. To further reduce the number of intercluster communications, heuristics for instruction replication are included. The proposed scheme is evaluated using the SPECfp95 programs. The described scheme outperforms a state-of-the-art scheduler for all programs and different cluster configurations. For some configurations, the speedup obtained when using this new scheme is greater than 40 percent, and for selected programs, performance can be more than doubled. |
dc.format.extent | 14 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Microprocessors |
dc.subject.lcsh | Graph theory |
dc.subject.other | Clustered microarchitectures |
dc.subject.other | ILP |
dc.subject.other | Instruction replication |
dc.subject.other | Modulo scheduling |
dc.subject.other | Statically scheduled processors |
dc.title | AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures |
dc.type | Article |
dc.subject.lemac | Microprocessadors |
dc.subject.lemac | Grafs, Teoria de |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/TC.2009.32 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4785457 |
dc.rights.access | Open Access |
local.identifier.drac | 1658657 |
dc.description.version | Postprint (published version) |
local.citation.author | Aleta, A.; Codina, J.M.; Sánchez, F.; González, A.; Kaeli, D. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 58 |
local.citation.number | 6 |
local.citation.startingPage | 770 |
local.citation.endingPage | 783 |
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