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dc.contributor.authorGonzález González, José
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2016-10-27T07:10:53Z
dc.date.available2016-10-27T07:10:53Z
dc.date.issued1999
dc.identifier.citationGonzález, J., González, A. Control-flow speculation through value prediction for superscalar processors. A: International Conference on Parallel Architectures and Compilation Techniques. "1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings". Newport Beach, California: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 57-65.
dc.identifier.isbn0-7695-0425-6
dc.identifier.urihttp://hdl.handle.net/2117/91141
dc.description.abstractIn this paper, we introduce a new branch predictor that predicts the outcomes of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The design of a hybrid predictor comprising our branch predictor and a correlating branch predictor is presented. We also propose a new selector that chooses the most reliable prediction for each branch. This selector is based on the path followed to reach the branch. Results for immediate updates show a significant improvement with respect to a conventional hybrid predictor for different size configurations. In addition, the proposed hybrid predictor with a size of 8 KB achieves the same miss ratio as a conventional one of 64 KB. Performance evaluation for a dynamically-scheduled superscalar processor, with realistic updates, shows a speed-up of 11% despite its higher latency (up to 4 cycles)
dc.format.extent9 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherParallel architectures
dc.subject.otherPerformance evaluation
dc.titleControl-flow speculation through value prediction for superscalar processors
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/PACT.1999.807406
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
local.identifier.drac2338475
dc.description.versionPostprint (published version)
local.citation.authorGonzález, J.; González, A.
local.citation.contributorInternational Conference on Parallel Architectures and Compilation Techniques
local.citation.pubplaceNewport Beach, California
local.citation.publicationName1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings
local.citation.startingPage57
local.citation.endingPage65


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