Control-flow speculation through value prediction for superscalar processors
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
In this paper, we introduce a new branch predictor that predicts the outcomes of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The design of a hybrid predictor comprising our branch predictor and a correlating branch predictor is presented. We also propose a new selector that chooses the most reliable prediction for each branch. This selector is based on the path followed to reach the branch. Results for immediate updates show a significant improvement with respect to a conventional hybrid predictor for different size configurations. In addition, the proposed hybrid predictor with a size of 8 KB achieves the same miss ratio as a conventional one of 64 KB. Performance evaluation for a dynamically-scheduled superscalar processor, with realistic updates, shows a speed-up of 11% despite its higher latency (up to 4 cycles)
CitationGonzález, J., González, A. Control-flow speculation through value prediction for superscalar processors. A: International Conference on Parallel Architectures and Compilation Techniques. "1999 International Conference on Parallel Architectures and Compilation Techniques: October 12-16, 1999, Newport Beach, California: proceedings". Newport Beach, California: Institute of Electrical and Electronics Engineers (IEEE), 1999, p. 57-65.