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WiSync: an architecture for fast synchronization through on-chip wireless communication
dc.contributor.author | Abadal Cavallé, Sergi |
dc.contributor.author | Cabellos Aparicio, Alberto |
dc.contributor.author | Alarcón Cot, Eduardo José |
dc.contributor.author | Torrellas, Josep |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2016-10-21T15:57:01Z |
dc.date.available | 2016-10-21T15:57:01Z |
dc.date.issued | 2016-04-01 |
dc.identifier.citation | Abadal, S., Albert Cabellos-Aparicio, Alarcon, E., Torrellas, J. WiSync: an architecture for fast synchronization through on-chip wireless communication. "ACM SIGPLAN notices", 1 Abril 2016, vol. 51, núm. 4, p. 3-17. |
dc.identifier.issn | 0362-1340 |
dc.identifier.uri | http://hdl.handle.net/2117/90954 |
dc.description.abstract | In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support.; In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors |
dc.subject.lcsh | Wireless LANs |
dc.subject.other | On-chip wireless communication |
dc.subject.other | Synchronization |
dc.subject.other | Massive multicore architectures |
dc.subject.other | Barrier synchronization |
dc.subject.other | Integrated-circuits |
dc.subject.other | CMOS |
dc.subject.other | Multiprocessors |
dc.subject.other | NOC |
dc.subject.other | Interconnects |
dc.subject.other | Challenges |
dc.subject.other | Networks |
dc.subject.other | Design |
dc.title | WiSync: an architecture for fast synchronization through on-chip wireless communication |
dc.type | Article |
dc.subject.lemac | Xarxes locals sense fil Wi-Fi |
dc.contributor.group | Universitat Politècnica de Catalunya. CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla |
dc.contributor.group | Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits |
dc.identifier.doi | 10.1145/2872362.2872396 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://dl.acm.org/citation.cfm?doid=2872362.2872396 |
dc.rights.access | Open Access |
local.identifier.drac | 18821835 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//PCIN-2015-012/ES/HACIA LAS COMUNICACIONES RF BASADAS EN GRAFENO ? DEMOSTRANDO LAS ANTENAS DE GRAFENO THZ PLASMONICAS./ |
local.citation.author | Abadal, S.; Cabellos-Aparicio, Albert; Alarcon, E.; Torrellas, J. |
local.citation.publicationName | ACM SIGPLAN notices |
local.citation.volume | 51 |
local.citation.number | 4 |
local.citation.startingPage | 3 |
local.citation.endingPage | 17 |
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