WiSync: an architecture for fast synchronization through on-chip wireless communication
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hdl:2117/90954
Tipus de documentArticle
Data publicació2016-04-01
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Abstract
In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support.; In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.
CitacióAbadal, S., Albert Cabellos-Aparicio, Alarcon, E., Torrellas, J. WiSync: an architecture for fast synchronization through on-chip wireless communication. "ACM SIGPLAN notices", 1 Abril 2016, vol. 51, núm. 4, p. 3-17.
ISSN0362-1340
Versió de l'editorhttp://dl.acm.org/citation.cfm?doid=2872362.2872396
Col·leccions
- Departament d'Arquitectura de Computadors - Articles de revista [1.046]
- Departament d'Enginyeria Electrònica - Articles de revista [1.713]
- EPIC - Energy Processing and Integrated Circuits - Articles de revista [216]
- CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla - Articles de revista [154]
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