POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core
Document typeConference lecture
Rights accessOpen Access
European Commission's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
In the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly energy-efficient way to increase performance; however adding support for them incurs area and power overheads that would not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design for the ARM architecture that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions together to execute them in a coordinated manner.
CitationStanic, Milan [et al.]. POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. A: 2016 International Conference on Parallel Architectures and Compilation. "PACT '16 Proceedings of the 2016 International Conference on Parallel Architectures and Compilation". ACM, 2016, p. 447-448.
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