Improving early design stage timing modeling in multicore based real-time systems
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Cita com:
hdl:2117/90179
Tipus de documentText en actes de congrés
Data publicació2016
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - and in particular it predicts the contention tasks suffer in the access to multicore on-chip shared resources. The model
presents the key properties of not requiring the application's source code or binary and having high-accuracy and low overhead. The former is of paramount importance in those common scenarios in which several software suppliers work in parallel implementing different applications for a system integrator, subject to different intellectual property (IP) constraints. Our model helps reducing the risk of exceeding the assigned budgets for each application in late design
stages and its associated costs.
CitacióTrilla, D., Jalle, J., Fernández, M., Abella, J., Cazorla, F. Improving early design stage timing modeling in multicore based real-time systems. A: IEEE Real-Time and Embedded Technology and Applications Symposium. "2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS): 11-14 April 2016: Vienna, Austria: proceedings". Vienna: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-12.
ISBN9781467386395
Versió de l'editorhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7461338
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