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Modelling Contention in Multicore Hardware Resources during Early Design Stages of Real-Time Systems
dc.contributor | Abella Ferrer, Jaume |
dc.contributor | Valero Cortés, Mateo |
dc.contributor | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Trilla Rodríguez, David |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2016-09-16T10:54:23Z |
dc.date.available | 2016-09-16T10:54:23Z |
dc.date.issued | 2016-07 |
dc.identifier.uri | http://hdl.handle.net/2117/89978 |
dc.description.abstract | This thesis presents a modelling approach for the timing behavior of real-time embedded systems in early design phases. The model focuses on multicore processors and it predicts the contention tasks suffer in the access to multicore on-chip shared resources. |
dc.language.iso | eng |
dc.publisher | Universitat Politècnica de Catalunya |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject.lcsh | Computer architecture |
dc.subject.lcsh | Real-time data processing |
dc.subject.other | sistemes |
dc.subject.other | temps |
dc.subject.other | real |
dc.subject.other | multicore |
dc.subject.other | interferencia |
dc.subject.other | anàlisi |
dc.subject.other | temporal |
dc.subject.other | disseny |
dc.subject.other | encastats |
dc.subject.other | real-time |
dc.subject.other | early |
dc.subject.other | design |
dc.subject.other | phases |
dc.subject.other | contention |
dc.subject.other | modeling |
dc.subject.other | timing |
dc.subject.other | analysis |
dc.subject.other | inter-task |
dc.subject.other | interference |
dc.subject.other | embedded |
dc.subject.other | systems |
dc.title | Modelling Contention in Multicore Hardware Resources during Early Design Stages of Real-Time Systems |
dc.type | Master thesis |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.subject.lemac | Temps real (Informàtica) |
dc.identifier.slug | 118461 |
dc.rights.access | Open Access |
dc.date.updated | 2016-07-09T04:00:09Z |
dc.audience.educationlevel | Màster |
dc.audience.mediator | Facultat d'Informàtica de Barcelona |
dc.audience.degree | MÀSTER UNIVERSITARI EN INNOVACIÓ I RECERCA EN INFORMÀTICA (Pla 2012) |