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dc.contributor.authorYazdanpanah Ahmadabadi, Fahimeh
dc.contributor.authorÁlvarez Martínez, Carlos
dc.contributor.authorJiménez González, Daniel
dc.contributor.authorBadia Sala, Rosa Maria
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationYazdanpanah, F., Álvarez, C., Jiménez, D., Badia, Rosa M., Valero, M. Picos: A hardware runtime architecture support for OmpSs. "Future generation computer systems", Desembre 2015, vol. 53, p. 130-139.
dc.description.abstractOmpSs is a programming model that provides a simple and powerful way of annotating sequential programs to exploit heterogeneity and task parallelism based on runtime data dependency analysis, dataflow scheduling and out-of-order task execution; it has greatly influenced Version 4.0 of the OpenMP standard. The current implementation of OmpSs achieves those capabilities with a pure-software runtime library: Nanos++. Therefore, although powerful and easy to use, the performance benefits of exploiting fine-grained (pico) task parallelism are limited by the software runtime overheads. To overcome this handicap we propose Picos, an implementation of the Task Superscalar (TSS) architecture that provides hardware support to the OmpSs programming model. Picos is a novel hardware dataflow-based task scheduler that dynamically analyzes inter-task dependencies and identifies task-level parallelism at run-time. In this paper, we describe the Picos Hardware Design and the latencies of the main functionality of its components, based on the synthesis of their VHDL design. We have implemented a full cycle-accurate simulator based on those latencies to perform a design exploration of the characteristics and number of its components in a reasonable amount of time. Finally, we present a comparison of the Picos and Nanos++ runtime performance scalability with a set of real benchmarks. With Picos, a programmer can achieve ideal scalability using aggressive parallel strategies with a large number of fine granularity tasks.
dc.description.sponsorshipThis work is supported by the Spanish Government through Programa Severo Ochoa (SEV-2011-0067), by the Spanish Ministry of Science and Technology through TIN2012-34557 project, by the Generalitat de Catalunya (contract 2009-SGR-980), by the European FP7 project TERAFLUX id. 249013 and by the European Research Council under the European Union’s 7th FP, ERC Grant Agreement number 321253. We also thank the Xilinx University Program for its hardware and software donations.
dc.format.extent10 p.
dc.rightsAttribution-NonCommercial-NoDerivs 4.0 International License
dc.subjectÀrees temàtiques de la UPC::Informàtica::Programació
dc.subject.lcshParallel programming (Computer science)
dc.subject.otherHardware implementation
dc.subject.otherTask scheduling
dc.subject.otherDataflow execution
dc.subject.otherParallel programming model
dc.titlePicos: A hardware runtime architecture support for OmpSs
dc.subject.lemacProgramació en paral·lel (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/249013/EU/Exploiting dataflow parallelism in Teradevice Computing/TERAFLUX
upcommons.citation.authorYazdanpanah, F.; Álvarez, C.; Jiménez, D.; Badia, Rosa M.; Valero, M.
upcommons.citation.publicationNameFuture generation computer systems

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