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dc.contributorSerra Graells, Francesc
dc.contributorDei, Michele
dc.contributorAragonès Cervera, Xavier
dc.contributor.authorCisneros Fernández, Jose Agustin
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-09-09T13:32:21Z
dc.date.available2016-09-09T13:32:21Z
dc.date.issued2016-07-18
dc.identifier.urihttp://hdl.handle.net/2117/89800
dc.descriptionThis Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB Op
dc.description.abstractA general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach.
dc.language.isoeng
dc.publisherUniversitat Politècnica de Catalunya
dc.rightsS'autoritza la difusió de l'obra mitjançant la llicència Creative Commons o similar 'Reconeixement-NoComercial- SenseObraDerivada'
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació
dc.subject.lcshAnalog-to-digital converters
dc.subject.other16 Bits
dc.subject.other50 kHz
dc.subject.otherLow-Power
dc.subject.otherLow-Distortion
dc.subject.otherNo boostrapping
dc.subject.otherSwitched Capacitor Sigma-Delta modulator.
dc.titleDesign of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technology
dc.typeMaster thesis
dc.subject.lemacConvertidors analògic/digitals
dc.identifier.slugETSETB-230.118879
dc.rights.accessOpen Access
dc.date.updated2016-08-17T11:16:27Z
dc.audience.educationlevelMàster
dc.audience.mediatorEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona


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