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Design of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technology

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[JCF]Design of a 16-bit 50-kHz Low-Power SC Delta-Sigma Modulator for ADC in 0.18um CMOS Technology.pdf (51,37Mb)
[JCF]Design_of_a_16-bit_50-kHz_Low-Power_SC_Delta-Sigma_Modulator_for_ADC_in_0.18um_CMOS_Technology.pdf (3,603Mb)
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hdl:2117/89800

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Cisneros Fernández, Jose Agustin
Tutor / directorSerra Graells, Francesc; Dei, Michele; Aragonès Cervera, XavierMés informacióMés informacióMés informació
Document typeMaster thesis
Date2016-07-18
Rights accessOpen Access
Attribution-NonCommercial-NoDerivs 3.0 Spain
This work is protected by the corresponding intellectual and industrial property rights. Except where otherwise noted, its contents are licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain
Abstract
A general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach.
Description
This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB Op
SubjectsAnalog-to-digital converters, Convertidors analògic/digitals
URIhttp://hdl.handle.net/2117/89800
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  • Màsters oficials - Master's degree in Electronic Engineering (MEE) [288]
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[JCF]Design of ... 0.18um CMOS Technology.pdf51,37MbPDFView/Open
[JCF]Design_of_ ... 0.18um_CMOS_Technology.pdf3,603MbPDFView/Open

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