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dc.contributor.authorValero García, Miguel
dc.contributor.authorNavarro Guerrero, Juan José
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherFacultat d'Informàtica de Barcelona
dc.date.accessioned2010-09-15T15:59:26Z
dc.date.available2010-09-15T15:59:26Z
dc.date.created1988
dc.date.issued1988
dc.identifier.citationValero-García, M; Navarro, J.; Llaberia, J.; Valero, M. Systematic design of two level pipelined systolic arrays with data contraflow. A: IEEE International Symposium on Circuits and Systems. "1988 IEEE International Symposium on Circuits and Systems: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1988, p. 2521-2525.
dc.identifier.isbn951-721-239-9
dc.identifier.urihttp://hdl.handle.net/2117/8885
dc.description.abstractMany systolic algorithms and related design methodologies have been recently proposed. Frecuently, in these systolic algorithms practical considerations are not taken into account. Equitatively distributed load between processing elements, pipelined functional units etc, are desirable features when implementing systolic algorithms.In this paper we present a design methodology in which these features are considered. As an example, the methodology is applied to obtain a problem-size-independent, two-level pipelined 1D systolic algorithm with data contraflow to efficiently solve triangular systems of equations.
dc.format.extent5 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshPipelining (Electronics)
dc.titleSystematic design of two level pipelined systolic arrays with data contraflow
dc.typeConference report
dc.subject.lemacProcessadors de matrius (arrays)
dc.contributor.groupUniversitat Politècnica de Catalunya. ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ISCAS.1988.15455
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/15455/
dc.rights.accessOpen Access
local.identifier.drac2634553
dc.description.versionPostprint (published version)
local.citation.authorValero-García, M; Navarro, J.; Llaberia, J.; Valero, M.
local.citation.contributorIEEE International Symposium on Circuits and Systems
local.citation.publicationName1988 IEEE International Symposium on Circuits and Systems: proceedings
local.citation.startingPage2521
local.citation.endingPage2525


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