Systematic design of two level pipelined systolic arrays with data contraflow
Document typeConference report
Rights accessOpen Access
Many systolic algorithms and related design methodologies have been recently proposed. Frecuently, in these systolic algorithms practical considerations are not taken into account. Equitatively distributed load between processing elements, pipelined functional units etc, are desirable features when implementing systolic algorithms.In this paper we present a design methodology in which these features are considered. As an example, the methodology is applied to obtain a problem-size-independent, two-level pipelined 1D systolic algorithm with data contraflow to efficiently solve triangular systems of equations.
CitationValero-García, M; Navarro, J.; Llaberia, J.; Valero, M. Systematic design of two level pipelined systolic arrays with data contraflow. A: IEEE International Symposium on Circuits and Systems. "1988 IEEE International Symposium on Circuits and Systems: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1988, p. 2521-2525.
- CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos 
- ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.612]
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