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dc.contributor.authorValero García, Miguel
dc.contributor.authorNavarro Guerrero, Juan José
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-09-15T15:47:46Z
dc.date.available2010-09-15T15:47:46Z
dc.date.created1990
dc.date.issued1990
dc.identifier.citationValero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M. Implementation of systolic algorithms using pipelined functional units. A: International Conference on Application Specific Array Processors. "Proceedings of the International Conference on Application Specific Array Processors". Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 272-283.
dc.identifier.urihttp://hdl.handle.net/2117/8884
dc.description.abstractThe authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of initiating a new operation before the previous one has been completed. The method permits transformation of a SA so that it can be efficiently executed using PFUs. The method is based on two temporal transformations (slowdown and retiming) and one spatial transformation (coalescing). The temporal transformations permit the modification of the SA in such a way that dependences established by the PFU are preserved. The spatial transformation improves the hardware utilization. The method was applied to 1-D SAs with data contraflow. To demonstrate the effectiveness of the method, the authors describe an efficient implementation of a non-time-homogeneous SA with data contraflow for QR decomposition
dc.format.extent12 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshPipelining (Electronics)
dc.subject.lcshSystolic array circuits
dc.titleImplementation of systolic algorithms using pipelined functional units
dc.typeConference report
dc.subject.lemacProcessadors de matrius (arrays)
dc.subject.lemacAlgorismes
dc.contributor.groupUniversitat Politècnica de Catalunya. ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ASAP.1990.145464
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/145464/
dc.rights.accessOpen Access
local.identifier.drac2634543
dc.description.versionPostprint (published version)
local.citation.authorValero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M.
local.citation.contributorInternational Conference on Application Specific Array Processors
local.citation.publicationNameProceedings of the International Conference on Application Specific Array Processors
local.citation.startingPage272
local.citation.endingPage283


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