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dc.contributor.authorGarcía Leyva, Lancelot
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.identifier.citationGarcía, L. [et al.]. Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits. A: IEEE international Midwest Symposium on Circuits and Systems. "53rd IEEE international Midwest Symposium on Circuits and Systems". Seattle, WA,: IEEE Press. Institute of Electrical and Electronics Engineers, 2010, p. 1101-1104.
dc.description.abstractAs devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.
dc.format.extent4 p.
dc.publisherIEEE Press. Institute of Electrical and Electronics Engineers
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject.lcshNanoscale electronic devices
dc.titleTurtle Logic: A new probabilistic design methodology of nanoscale digital circuits
dc.typeConference report
dc.subject.lemacCircuits digitals -- Disseny
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
local.citation.authorGarcía, L.; Calomarde, A.; Moll, F.; Rubio, J.
local.citation.contributorIEEE international Midwest Symposium on Circuits and Systems
local.citation.pubplaceSeattle, WA,
local.citation.publicationName53rd IEEE international Midwest Symposium on Circuits and Systems

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