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Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits

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10.1109/MWSCAS.2010.5548845
 
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García Leyva, Lancelot
Calomarde Palomino, AntonioMés informacióMés informacióMés informació
Moll Echeto, Francisco de BorjaMés informacióMés informacióMés informació
Rubio Sola, Jose AntonioMés informacióMés informacióMés informació
Document typeConference report
Defense date2010
PublisherIEEE Press. Institute of Electrical and Electronics Engineers
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.
CitationGarcía, L. [et al.]. Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits. A: IEEE international Midwest Symposium on Circuits and Systems. "53rd IEEE international Midwest Symposium on Circuits and Systems". Seattle, WA,: IEEE Press. Institute of Electrical and Electronics Engineers, 2010, p. 1101-1104. 
URIhttp://hdl.handle.net/2117/8873
DOI10.1109/MWSCAS.2010.5548845
Publisher versionhttp://ieeexplore.ieee.org/search/searchresult.jsp?newsearch=true&queryText=10.1109%2FMWSCAS.2010.5548845&x=50&y=19&tag=1
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