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High-Level Debugging and Verification for FPGA-Based Multicore Architectures
dc.contributor.author | Arcas, Oriol |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Unsal, Osman S. |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2016-07-07T10:48:54Z |
dc.date.available | 2016-07-07T10:48:54Z |
dc.date.issued | 2015-05-05 |
dc.identifier.citation | Arcas, Oriol; Cristal, Adrian; Unsal, Osman S. High-Level Debugging and Verification for FPGA-Based Multicore Architectures. A: 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, BC, 2-6 May 2015. "Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on". Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 135-142. |
dc.identifier.uri | http://hdl.handle.net/2117/88604 |
dc.description.abstract | Simulators are key tools for computer architecture research. However, multicore architectures represent a highly complex challenge for software simulators, which may suffer from fidelity loss and long execution times. FPGAs can simulate multicore architectures with scalable performance and high accuracy, but the difficulty of debugging could hinder their adoption. In this paper we propose several techniques for inspection, debugging and verification of multicore architectures, both for software-based and FPGA-based simulations. These debugging extensions are cycle-accurate and unobtrusive. As a proof of concept, we have developed a 24-core RISC multiprocessor that runs the Linux Kernel, for which we provide three simulation modes: a fast, functional simulation; a detailed, cycle-accurate simulation; and a FPGA-based simulation. Our platform can run up to 24 cores and perform full-system verification at 17 million instructions per second. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Debugging in computer science |
dc.subject.lcsh | Computer architecture |
dc.subject.lcsh | FPGA |
dc.subject.lcsh | Computer simulation |
dc.subject.other | FPGA |
dc.subject.other | Debugging |
dc.subject.other | Verification |
dc.subject.other | Multicore |
dc.title | High-Level Debugging and Verification for FPGA-Based Multicore Architectures |
dc.type | Conference lecture |
dc.subject.lemac | Simulació, Mètodes de |
dc.subject.lemac | Simulació per ordinador |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.identifier.doi | 10.1109/FCCM.2015.14 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7160057&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D7160057 |
dc.rights.access | Open Access |
dc.description.version | Postprint (author's final draft) |
local.citation.contributor | 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, BC, 2-6 May 2015 |
local.citation.publicationName | Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on |
local.citation.startingPage | 135 |
local.citation.endingPage | 142 |