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dc.contributor.authorFerrerón, Alexandra
dc.contributor.authorSuárez Gracia, Darío
dc.contributor.authorAlastruey, Jesús
dc.contributor.authorMonreal Arnal, Teresa
dc.contributor.authorIbáñez, Pablo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationFerrerón, A., Suárez, D., Alastruey, J., Monreal, T., Ibáñez, P. Concertina: Squeezing in cache content to operate at near-threshold voltage. "IEEE transactions on computers", 01 Març 2016, vol. 65, núm. 3, p. 755-769.
dc.description© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractScaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100 percent of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression- and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2 percent, even when using small SRAM cells, which implies over 90 percent of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.
dc.format.extent15 p.
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshTelecommunication -- Energy conservation
dc.subject.otherNear-threshold voltage
dc.subject.otherSRAM variability
dc.subject.otherOn-chip caches
dc.titleConcertina: Squeezing in cache content to operate at near-threshold voltage
dc.subject.lemacTelecomunicació -- Estalvi d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
upcommons.citation.authorFerrerón, A.; Suárez, D.; Alastruey, J.; Monreal, T.; Ibáñez, P.
upcommons.citation.publicationNameIEEE transactions on computers

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