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Runtime-aware architectures
dc.contributor.author | Casas, Marc |
dc.contributor.author | Moretó Planas, Miquel |
dc.contributor.author | Álvarez Martí, Lluc |
dc.contributor.author | Castillo Villar, Emilio |
dc.contributor.author | Chasapis, Dimitrios |
dc.contributor.author | Hayes, Timothy |
dc.contributor.author | Jaulmes, Luc |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2016-07-04T11:25:13Z |
dc.date.available | 2016-08-01T00:30:38Z |
dc.date.issued | 2015 |
dc.identifier.citation | Casas, M., Moreto, M., Álvarez, Ll., Castillo, E., Chasapis, D., Hayes, T., Jaulmes, L., Palomar, Ó., Unsal, O., Cristal, A., Ayguadé, E., Labarta, J., Valero, M. Runtime-aware architectures. A: International European Conference on Parallel and Distributed Computing. "Euro-Par 2015: Parallel Processing: 21st International Conference on Parallel and Distributed Computing, Vienna, Austria, August 24-28, 2015: proceedings". Viena: Springer, 2015, p. 16-27. |
dc.identifier.isbn | 978-3-662-48096-0 |
dc.identifier.uri | http://hdl.handle.net/2117/88483 |
dc.description.abstract | In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores face. The runtime system of the parallel programming model has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In the paper, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime’s perspective. |
dc.description.sponsorship | This work has been partially supported by the European Research Council under the European Union’s 7th FP, ERC Grant Agreement number 321253, by the Spanish Ministry of Science and Innovation under grant TIN2012-34557 and by the HiPEAC Network of Excellence. M. Moreto has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI- 2012-15047, and M. Casas is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Co-fund programme of the Marie Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP B 00243). |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.publisher | Springer |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Multiprocessors |
dc.subject.lcsh | Parallel programming (Computer science) |
dc.subject.other | Multiprocessing systems |
dc.subject.other | Parallel architectures |
dc.subject.other | Parallel programming |
dc.title | Runtime-aware architectures |
dc.type | Conference report |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Programació en paral·lel (Informàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1007/978-3-662-48096-0_2 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://dx.doi.org/10.1007/978-3-662-48096-0_2 |
dc.rights.access | Open Access |
local.identifier.drac | 17530793 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
local.citation.author | Casas, M.; Moreto, M.; Álvarez, Ll.; Castillo, E.; Chasapis, D.; Hayes, T.; Jaulmes, L.; Palomar, Ó.; Unsal, O.; Cristal, A.; Ayguadé, E.; Labarta, J.; Valero, M. |
local.citation.contributor | International European Conference on Parallel and Distributed Computing |
local.citation.pubplace | Viena |
local.citation.publicationName | Euro-Par 2015: Parallel Processing: 21st International Conference on Parallel and Distributed Computing, Vienna, Austria, August 24-28, 2015: proceedings |
local.citation.startingPage | 16 |
local.citation.endingPage | 27 |