Show simple item record

dc.contributor.authorArumi Delgado, Daniel
dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorFigueras, Joan
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-05-06T12:45:36Z
dc.date.available2016-05-06T12:45:36Z
dc.date.issued2015-09-24
dc.identifier.citationArumi, D., Rodriguez, R., Figueras, J. Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents. "IEEE transactions on very large scale integration (VLSI) systems", 24 Setembre 2015, vol. 24, núm. 5, p. 1739-1748.
dc.identifier.issn1063-8210
dc.identifier.urihttp://hdl.handle.net/2117/86699
dc.description.abstractIntragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.
dc.format.extent10 p.
dc.language.isoeng
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshIntegrated circuits--Verification
dc.subject.otherIntegrated circuit (IC) testing
dc.subject.otherleakage currents
dc.subject.otherparasitic capacitances
dc.subject.otherstuck-open faults (SOFs)
dc.subject.othertest escapes
dc.titleTest escapes of stuck-open faults caused by parasitic capacitances and leakage currents
dc.typeArticle
dc.subject.lemacCircuits integrats -- Verificació
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.doi10.1109/TVLSI.2015.2477103
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275171
dc.rights.accessOpen Access
drac.iddocument17692377
dc.description.versionPostprint (published version)
upcommons.citation.authorArumi, D., Rodriguez, R., Figueras, J.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on very large scale integration (VLSI) systems
upcommons.citation.volume24
upcommons.citation.number5
upcommons.citation.startingPage1739
upcommons.citation.endingPage1748


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain