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dc.contributor.authorPérez Puigdemont, Jordi
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-05-05T12:18:55Z
dc.date.available2016-05-05T12:18:55Z
dc.date.issued2012
dc.identifier.citationPerez, J., Calomarde, A., Moll, F. Variation tolerant self-adaptive clock generation architecture based on a ring oscillator. A: IEEE International System On Chip Conference. "SOC Conference (SOCC), 2012 IEEE International". Niagara Falls, NY: Institute of Electrical and Electronics Engineers (IEEE), 2012, p. 387-392.
dc.identifier.isbn978-1-4673-1295-0
dc.identifier.urihttp://hdl.handle.net/2117/86639
dc.description.abstractIn this work we propose a self-adaptive clock based on a ring oscillator as the solution for the increasing uncertainty in the critical path delay. This increase in uncertainty forces to add more safety margins to the clock period which produces a circuit performance downgrade. We evaluate three self-adaptive clock systems: free running ring oscillator, infinite impulse response filter controlled RO and TEAtime controlled ring oscillator. The safety margin reduction of the three alternatives is investigated under different clock distribution delay conditions, dynamic variation frequencies and the presence of mismatch between the ring oscillator and the critical paths and the delay sensors.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshClocks and watches)
dc.subject.lcshTime measurements
dc.titleVariation tolerant self-adaptive clock generation architecture based on a ring oscillator
dc.typeConference lecture
dc.subject.lemacRellotges
dc.subject.lemacCronometria
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/SOCC.2012.6398341
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6398341&contentType=Conference+Publications&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6398324%29%26pageNumber%3D4
dc.rights.accessOpen Access
local.identifier.drac11211783
dc.description.versionPostprint (published version)
local.citation.authorPerez, J.; Calomarde, A.; Moll, F.
local.citation.contributorIEEE International System On Chip Conference
local.citation.pubplaceNiagara Falls, NY
local.citation.publicationNameSOC Conference (SOCC), 2012 IEEE International
local.citation.startingPage387
local.citation.endingPage392


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