Hardware-Accelerated neural network

Expósito Piñol, Luis

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Expósito Piñol, Luis

Tutor / director / evaluatorCanal Corretger, Ramon

; Cruz Díaz, Josep Llorenç

Document typeMaster thesis

Date2016-04-21

Rights accessOpen Access

Abstract

This work presents a parametrizable design of a neural network on an FPGA, being trained previously in the CPU using backpropagation. We test different configurations and report delay, power and area.

SubjectsNeural networks (Computer science), Field programmable gate arrays, Xarxes neuronals (Informàtica), Matrius de portes programables in situ

URIhttp://hdl.handle.net/2117/86176

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Màsters Oficials - Master in Innovation and Research in Informatics - MIRI [229]

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