Hardware-Accelerated neural network

Expósito Piñol, Luis

View/Open

113022.pdf (1,862Mb)

View Usage Statistics

Show full item record

Expósito Piñol, Luis

Tutor / director / evaluatorCanal Corretger, Ramon

; Cruz Díaz, Josep Llorenç

Document typeMaster thesis

Date2016-04-21

Rights accessOpen Access

Abstract

This work presents a parametrizable design of a neural network on an FPGA, being trained previously in the CPU using backpropagation. We test different configurations and report delay, power and area.

SubjectsNeural networks (Computer science), Field programmable gate arrays, Xarxes neuronals (Informàtica), Matrius de portes programables in situ

URIhttp://hdl.handle.net/2117/86176

Collections

Màsters Oficials - Master in Innovation and Research in Informatics - MIRI [199]

View Usage Statistics

Show full item record

Files	Description	Size	Format	View
113022.pdf		1,862Mb	PDF	View/Open

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder

UPCommons. Global access to UPC knowledge