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Reusing cached schedules in an out-of-order processor with in-order issue logic
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Juan, Toni |
dc.contributor.author | Navarro Guerrero, Juan José |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2010-08-03T09:44:50Z |
dc.date.available | 2010-08-03T09:44:50Z |
dc.date.created | 2009 |
dc.date.issued | 2009 |
dc.identifier.citation | Palomar, O.; Toni Juan; Navarro, J. Reusing cached schedules in an out-of-order processor with in-order issue logic. A: IEEE International Conference on Computer Design. "XXVII International Conference on Computer Design". 2009, p. 246-253. |
dc.identifier.isbn | 978-1-4244-5028-2 |
dc.identifier.uri | http://hdl.handle.net/2117/8563 |
dc.description.abstract | The complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue logic belongs to just 13% of the total different groups issued: the issue logic of an out-of-order processor is constantly re-discovering what it has already found. To benefit from the repetitive nature of instruction issue, we move the scheduling logic after the commit stage, out of the critical path of execution. The schedules created there are cached and reused to feed a simple in-order issue logic, that could result in a higher frequency design. We present the complete design of our ReLaSch processor, that achieves the same average IPC than a conventional out-of-order processor, and a 1.56 speed-up over the IPC of an in-order processor. We actually surpass the out-of-order IPC in 23 out of 40 SPEC benchmarks, mainly because the broader vision of the code after the commit stage allows creating better schedules. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Aplicacions de la informàtica::Disseny assistit per ordinador |
dc.subject.lcsh | Cache memory |
dc.subject.lcsh | Logic circuits |
dc.subject.lcsh | Out-of-order processor |
dc.subject.lcsh | In-order issue logic |
dc.title | Reusing cached schedules in an out-of-order processor with in-order issue logic |
dc.type | Conference report |
dc.subject.lemac | Memòria cau |
dc.subject.lemac | Circuits lògics |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/ICCD.2009.5413146 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Open Access |
local.identifier.drac | 2561411 |
dc.description.version | Postprint (published version) |
local.citation.author | Palomar, O.; Toni Juan; Navarro, J. |
local.citation.contributor | IEEE International Conference on Computer Design |
local.citation.publicationName | XXVII International Conference on Computer Design |
local.citation.startingPage | 246 |
local.citation.endingPage | 253 |