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dc.contributor.authorPalomar Pérez, Óscar
dc.contributor.authorJuan, Toni
dc.contributor.authorNavarro Guerrero, Juan José
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-08-03T09:44:50Z
dc.date.available2010-08-03T09:44:50Z
dc.date.created2009
dc.date.issued2009
dc.identifier.citationPalomar, O.; Toni Juan; Navarro, J. Reusing cached schedules in an out-of-order processor with in-order issue logic. A: IEEE International Conference on Computer Design. "XXVII International Conference on Computer Design". 2009, p. 246-253.
dc.identifier.isbn978-1-4244-5028-2
dc.identifier.urihttp://hdl.handle.net/2117/8563
dc.description.abstractThe complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue logic belongs to just 13% of the total different groups issued: the issue logic of an out-of-order processor is constantly re-discovering what it has already found. To benefit from the repetitive nature of instruction issue, we move the scheduling logic after the commit stage, out of the critical path of execution. The schedules created there are cached and reused to feed a simple in-order issue logic, that could result in a higher frequency design. We present the complete design of our ReLaSch processor, that achieves the same average IPC than a conventional out-of-order processor, and a 1.56 speed-up over the IPC of an in-order processor. We actually surpass the out-of-order IPC in 23 out of 40 SPEC benchmarks, mainly because the broader vision of the code after the commit stage allows creating better schedules.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Aplicacions de la informàtica::Disseny assistit per ordinador
dc.subject.lcshCache memory
dc.subject.lcshLogic circuits
dc.subject.lcshOut-of-order processor
dc.subject.lcshIn-order issue logic
dc.titleReusing cached schedules in an out-of-order processor with in-order issue logic
dc.typeConference report
dc.subject.lemacMemòria cau
dc.subject.lemacCircuits lògics
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ICCD.2009.5413146
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
local.identifier.drac2561411
dc.description.versionPostprint (published version)
local.citation.authorPalomar, O.; Toni Juan; Navarro, J.
local.citation.contributorIEEE International Conference on Computer Design
local.citation.publicationNameXXVII International Conference on Computer Design
local.citation.startingPage246
local.citation.endingPage253


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