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dc.contributor.authorÁlvarez Martí, Lluc
dc.contributor.authorVilanova, Lluís
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorCasas, Marc
dc.contributor.authorGonzález Tallada, Marc
dc.contributor.authorMartorell Bofill, Xavier
dc.contributor.authorNavarro, Nacho
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2016-03-29T08:19:35Z
dc.date.available2016-03-29T08:19:35Z
dc.date.issued2015
dc.identifier.citationÁlvarez, Ll., Vilanova, L., Moreto, M., Casas, M., González, M., Martorell, X., Navarro, Nacho, Ayguadé, E., Valero, M. Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. A: International Symposium on Computer Architecture. "Proceedings of the 42nd Annual International Symposium on Computer Architecture". Portland, Oregon: Association for Computing Machinery (ACM), 2015, p. 720-732.
dc.identifier.isbn978-1-4503-3402-0
dc.identifier.urihttp://hdl.handle.net/2117/84775
dc.description.abstractThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a hybrid memory system. Scratchpad memories are more power-efficient than caches and they do not generate coherence traffic, but they suffer from poor programmability. A good way to hide the programmability difficulties to the programmer is to give the compiler the responsibility of generating code to manage the scratchpad memories. Unfortunately, compilers do not succeed in generating this code in the presence of random memory accesses with unknown aliasing hazards. This paper proposes a coherence protocol for the hybrid memory system that allows the compiler to always generate code to manage the scratchpad memories. In coordination with the compiler, memory accesses that may access stale copies of data are identified and diverted to the valid copy of the data. The proposal allows the architecture to be exposed to the programmer as a shared memory manycore, maintaining the programming simplicity of shared memory models and preserving backwards compatibility. In a 64-core manycore, the coherence protocol adds overheads of 4% in performance, 8% in network traffic and 9% in energy consumption to enable the usage of the hybrid memory system that, compared to a cache-based system, achieves a speedup of 1.14x and reduces on-chip network traffic and energy consumption by 29% and 17%, respectively.
dc.description.sponsorshipThis work has been supported by the Spanish Government (grant SEV-2011-00067 of the Severo Ochoa Program), by the Spanish Ministry of Science and Innovation (contract TIN2012-34557), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), and by the RoMoL ERC Advanced Grant (GA 321253). Miquel Moreto has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047, and Marc Casas is supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the 7th R&D Framework Programme of the European Union (Contract 2013 BP_B 00243).
dc.format.extent13 p.
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshMemory management (Computer science)
dc.subject.lcshCache memory
dc.titleCoherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
dc.typeConference report
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacGestió de memòria (Informàtica)
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/2749469.2750411
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?id=2750411
dc.rights.accessOpen Access
drac.iddocument16694270
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2012-34557
dc.relation.projectidinfo:eu-repo/grantAgreement/SEV-2011-00067
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/JCI-2012-15047
upcommons.citation.authorÁlvarez, Ll.; Vilanova, L.; Moreto, M.; Casas, M.; González, M.; Martorell, X.; Navarro, Nacho; Ayguadé, E.; Valero, M.
upcommons.citation.contributorInternational Symposium on Computer Architecture
upcommons.citation.pubplacePortland, Oregon
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 42nd Annual International Symposium on Computer Architecture
upcommons.citation.startingPage720
upcommons.citation.endingPage732


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