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dc.contributor.authorDorta Pérez, Silvestre Taho
dc.contributor.authorZapata Rodríguez, Mireya
dc.contributor.authorMadrenas Boadas, Jordi
dc.contributor.authorSánchez Rivera, Giovanny
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-03-16T15:11:51Z
dc.date.available2016-03-16T15:11:51Z
dc.date.issued2016-01-01
dc.identifier.citationDorta, S., Zapata, M., Madrenas, J., Sanchez , G. AER-SRT: scalable spike distribution by means of synchronous serial ring topology address event representation. "Neurocomputing", 01 Gener 2016, vol. 171, p. 1684-1690.
dc.identifier.issn0925-2312
dc.identifier.urihttp://hdl.handle.net/2117/84521
dc.description.abstractGiven the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards. (C) 2015 Elsevier B.V. All rights reserved.
dc.format.extent7 p.
dc.language.isoeng
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Intel·ligència artificial
dc.subject.lcshNeural networks (Computer science)
dc.subject.otherAER (Address Event Representation)
dc.subject.otherMulti-chip communication
dc.subject.otherSynchronous serial ring
dc.subject.otherAurora protocol
dc.subject.otherSNN emulation
dc.subject.otherTime slot emulation
dc.subject.otherInfrastructure
dc.titleAER-SRT: scalable spike distribution by means of synchronous serial ring topology address event representation
dc.typeArticle
dc.subject.lemacOrdinadors neuronals
dc.contributor.groupUniversitat Politècnica de Catalunya. CETpD -Centre d'Estudis Tecnològics per a l'Atenció a la Dependència i la Vida Autònoma
dc.identifier.doi10.1016/j.neucom.2015.07.080
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ac.els-cdn.com/S0925231215010875/1-s2.0-S0925231215010875-main.pdf?_tid=9d9c730a-b943-11e5-bd69-00000aacb35f&acdnat=1452613756_2a4a41c3277480cbc07e09413e32b2eb
dc.rights.accessOpen Access
local.identifier.drac17363872
dc.description.versionPreprint
local.citation.authorDorta, S.; Zapata, M.; Madrenas, J.; Sanchez, G.
local.citation.publicationNameNeurocomputing
local.citation.volume171
local.citation.startingPage1684
local.citation.endingPage1690


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