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dc.contributor.authorSan Pedro Martín, Javier de
dc.contributor.authorCortadella, Jordi
dc.contributor.authorRoca Pérez, Antoni
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2016-03-15T12:16:59Z
dc.date.available2016-03-15T12:16:59Z
dc.date.issued2014
dc.identifier.citationDe San Pedro, J., Cortadella, J., Roca, A. A hierarchical approach for generating regular floorplans. A: IEEE/ACM International Conference on Computer Aided Design. "2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD): digest of technical papers:November 2-6, 2014: Hilton San Jose Hotel, San Jose, CA". San Jose, CA: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 655-662.
dc.identifier.isbn978-1-4799-6277-8
dc.identifier.urihttp://hdl.handle.net/2117/84370
dc.description© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
dc.description.abstractThe complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more reusable parts. In this work we introduce HiReg, a new floorplanning algorithm that generates regular floorplans. HiReg automatically extracts repeating patterns in a design by using graph mining techniques. Regularity is exploited by reusing the same floorplan for multiple instances of a pattern, as long as neither area, wire length or existing hierarchy constraints are violated or compromised. The proposed scheme is targeted towards early system-level design of chip multiprocessors (CMPs). Experiments show the scalability of the method for many-core CMPs and competitive results in area and wire length
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Aplicacions de la informàtica::Disseny assistit per ordinador
dc.subject.lcshIntegrated circuits--Very large scale integration
dc.titleA hierarchical approach for generating regular floorplans
dc.typeConference report
dc.subject.lemacCircuits integrats a molt gran escala
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/ICCAD.2014.7001422
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7001422
dc.rights.accessOpen Access
local.identifier.drac17509729
dc.description.versionPostprint (author's final draft)
local.citation.authorDe San Pedro, J.; Cortadella, J.; Roca, A.
local.citation.contributorIEEE/ACM International Conference on Computer Aided Design
local.citation.pubplaceSan Jose, CA
local.citation.publicationName2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD): digest of technical papers:November 2-6, 2014: Hilton San Jose Hotel, San Jose, CA
local.citation.startingPage655
local.citation.endingPage662


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