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dc.contributor.authorGómez Pau, Álvaro
dc.contributor.authorBalado Suárez, Luz María
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-02-19T20:01:28Z
dc.date.available2016-02-19T20:01:28Z
dc.date.issued2015
dc.identifier.citationÁlvaro Gómez-Pau, Balado, L., Figueras, J. Efficient production binning using octree tessellation in the alternate measurements space. "IEEE transactions on computer-aided design of integrated circuits and systems", 2015.
dc.identifier.issn0278-0070
dc.identifier.urihttp://hdl.handle.net/2117/83209
dc.description.abstractBinning after volume production is a widely accepted technique to classify fabricated ICs into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell non optimal devices at lower rates, so adapting to customer’s quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly non linear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this work functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases, the training phase and the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a SVM based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is 5X times faster using octrees than using the SVM based classifier.
dc.language.isoeng
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshSignal processing
dc.subject.lcshMixed signal circuits
dc.subject.otherBand-pass filters
dc.subject.otherIntegrated circuit modeling
dc.subject.otherOctrees
dc.subject.otherPerformance evaluation
dc.subject.otherProduction
dc.subject.otherTraining
dc.subject.otherAlternate Test
dc.subject.otherAnalog Filter
dc.subject.otherAnalog and Mixed-Signal Test
dc.subject.otherButterworth Filter
dc.subject.otherClassifiers
dc.subject.otherFeature Selection
dc.subject.otherProduction Binning
dc.subject.otherQuadtrees
dc.subject.otherQuality Binning
dc.subject.otherQuality Metrics
dc.subject.otherSignature Selection
dc.subject.otherSpecification Binning
dc.titleEfficient production binning using octree tessellation in the alternate measurements space
dc.typeArticle
dc.subject.lemacTractament del senyal
dc.subject.lemacCircuits integrats mixtos
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.doi10.1109/TCAD.2015.2501309
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7329977
dc.rights.accessOpen Access
local.identifier.drac17388367
dc.description.versionPostprint (author's final draft)
local.citation.authorGómez-Pau, Álvaro; Balado, L.; Figueras, J.
local.citation.publicationNameIEEE transactions on computer-aided design of integrated circuits and systems


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