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Efficient production binning using octree tessellation in the alternate measurements space
dc.contributor.author | Gómez Pau, Álvaro |
dc.contributor.author | Balado Suárez, Luz María |
dc.contributor.author | Figueras Pàmies, Joan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2016-02-19T20:01:28Z |
dc.date.available | 2016-02-19T20:01:28Z |
dc.date.issued | 2015 |
dc.identifier.citation | Álvaro Gómez-Pau, Balado, L., Figueras, J. Efficient production binning using octree tessellation in the alternate measurements space. "IEEE transactions on computer-aided design of integrated circuits and systems", 2015. |
dc.identifier.issn | 0278-0070 |
dc.identifier.uri | http://hdl.handle.net/2117/83209 |
dc.description.abstract | Binning after volume production is a widely accepted technique to classify fabricated ICs into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell non optimal devices at lower rates, so adapting to customer’s quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly non linear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this work functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases, the training phase and the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a SVM based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is 5X times faster using octrees than using the SVM based classifier. |
dc.language.iso | eng |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Signal processing |
dc.subject.lcsh | Mixed signal circuits |
dc.subject.other | Band-pass filters |
dc.subject.other | Integrated circuit modeling |
dc.subject.other | Octrees |
dc.subject.other | Performance evaluation |
dc.subject.other | Production |
dc.subject.other | Training |
dc.subject.other | Alternate Test |
dc.subject.other | Analog Filter |
dc.subject.other | Analog and Mixed-Signal Test |
dc.subject.other | Butterworth Filter |
dc.subject.other | Classifiers |
dc.subject.other | Feature Selection |
dc.subject.other | Production Binning |
dc.subject.other | Quadtrees |
dc.subject.other | Quality Binning |
dc.subject.other | Quality Metrics |
dc.subject.other | Signature Selection |
dc.subject.other | Specification Binning |
dc.title | Efficient production binning using octree tessellation in the alternate measurements space |
dc.type | Article |
dc.subject.lemac | Tractament del senyal |
dc.subject.lemac | Circuits integrats mixtos |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.identifier.doi | 10.1109/TCAD.2015.2501309 |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7329977 |
dc.rights.access | Open Access |
local.identifier.drac | 17388367 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Gómez-Pau, Álvaro; Balado, L.; Figueras, J. |
local.citation.publicationName | IEEE transactions on computer-aided design of integrated circuits and systems |
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