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dc.contributor.authorVatajelu, Elena Ioana
dc.contributor.authorRodríguez Montañés, Rosa
dc.contributor.authorIndaco, Marco
dc.contributor.authorPrinetto, Paolo
dc.contributor.authorFigueras Pàmies, Joan
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2016-02-18T18:42:54Z
dc.date.issued2015
dc.identifier.citationVatajelu, E., Rodriguez, R., Indaco, M., Paolo Prinetto, Figueras, J. STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. A: International Conference on Design & Technology of Integrated Systems in Nanoscale Era. "2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2015): Napoli, Italy: 21–23 April 2015". Napoli: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 1-6.
dc.identifier.isbn9781479920006
dc.identifier.urihttp://hdl.handle.net/2117/83144
dc.description.abstractThe CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshMagnetic memory (Computers)
dc.subject.otherreliability
dc.subject.otherprocess variation
dc.subject.othervoltage variation
dc.subject.othertemperature
dc.subject.otherSTT-MRAM cell
dc.subject.otherstatistical analysis
dc.titleSTT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations
dc.typeConference report
dc.subject.lemacMemòria magnètica (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.doi10.1109/DTIS.2015.7127377
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7127377
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac17409435
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorVatajelu, E.; Rodriguez, R.; Indaco, M.; Prinetto, Paolo; Figueras, J.
local.citation.contributorInternational Conference on Design & Technology of Integrated Systems in Nanoscale Era
local.citation.pubplaceNapoli
local.citation.publicationName2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2015): Napoli, Italy: 21–23 April 2015
local.citation.startingPage1
local.citation.endingPage6


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