STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations
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Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. For this reason, alternate solutions are being proposed in literature, to possibly replace charge based memories. One of the most promising of these solutions is the spin-transfer-torque magnetic random access memory (STT-MRAM). To evaluate the viability of such solution, one must understand how it behaves under the effect of the various reliability degradation factors. In this paper we propose a methodology which allows for fast reliability evaluation of an STT-MRAM cell under process, voltage, and temperature variations. Our proposed method allows for a sensitivity analysis which will show the designer/test engineer which is the main reliability concern of a certain design. The method is general, and it can be applied to any memory design.
CitationVatajelu, E., Rodriguez, R., Indaco, M., Paolo Prinetto, Figueras, J. STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. A: International Conference on Design & Technology of Integrated Systems in Nanoscale Era. "2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS 2015): Napoli, Italy: 21–23 April 2015". Napoli: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 1-6.