dc.contributor | Robert Sanxis, Francesc Josep |
dc.contributor.author | Ninou Herraiz, Jordi |
dc.date.accessioned | 2016-01-26T08:42:05Z |
dc.date.issued | 2015-06-23 |
dc.identifier.uri | http://hdl.handle.net/2117/82016 |
dc.description.abstract | The general objective of this project is to establish communication between a FPGA and a commercial piezo controller in order to govern a piezoelectric actuator for quick orientation and polarization stabilization of a laser beam. The control orientation and polarization stabilization of the laser beam, referred as Alice Phase Intensity, is part of the Fast project beam steering with full polarization control using a galvanometric optical scanner and polarization controller, manufactured by ICFO, Institute of Photonic Sciences. The main tasks of the project will be to think out, design and manufacture an electronic circuit that includes a CPLD to communicate between the Alice system FPGA and the actuator controller (MPD-001-4X). The circuit will also have the possibility to connect two additional devices as well as a UART (Universal Asynchronous Receiver-Transmitter) via a USB connection. This circuit will be referred to as Additional IO UART. The communication protocol between the CPLD and FPGA will be also addressed. The document is divided into different chapters. The first chapter explains the driver orientation and polarization of the laser. In the second chapter we review the general features of CPLDs and in particular the XC2C128-7VVQ100C from CoolRunner -II family model. The third chapter describes the design criteria of the the electronic circuit and manufacture of the PCB. The fourth chapter explains the Protocol created to establish communication between the different devices. Finally, chapter five presents simulations and tests as well as the conclusions that are drawn from the project. |
dc.language.iso | spa |
dc.publisher | Universitat Politècnica de Catalunya |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Electronics |
dc.subject.other | Xilinx FPGA i CPLD |
dc.subject.other | disseny i simulació de sistemes digitals amb VHDL |
dc.subject.other | actuador |
dc.subject.other | interficie entrada/sortida |
dc.subject.other | disseny de targetes de circuit imprès |
dc.subject.other | instrumentació electrònica digital |
dc.title | Disseny d'una interfície entre una targeta FPGA amb xips de Xilinx i actuadors General Photonics |
dc.type | Master thesis (pre-Bologna period) |
dc.subject.lemac | Electrònica digital |
dc.rights.access | Restricted access - author's decision |
dc.date.lift | 10000-01-01 |
dc.date.updated | 2015-06-27T06:39:42Z |
dc.audience.educationlevel | Estudis de primer/segon cicle |
dc.audience.mediator | Escola d'Enginyeria de Telecomunicació i Aeroespacial de Castelldefels |
dc.audience.degree | ENGINYERIA TÈCNICA DE TELECOMUNICACIÓ, ESPECIALITAT EN SISTEMES DE TELECOMUNICACIÓ (Pla 2000) |