Multicast on-Chip traffic analysis targeting manycore NoC design
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the many core era. Multicast support represents a particular yet relevant case within this context and has been the focus of different research efforts, mainly due to the poor performance of NoCs in the presence of this increasingly important type of traffic. However, most of the proposed schemes have been evaluated using synthetic traffic or within a full system, which is either unrealistic or costly. While traffic models would allow to better assess their performance, existing proposals do not distinguish between unicast and multicast flows and often are bound to a given number of cores. In this paper, a trace-based multicast traffic characterization is presented with the aim to provide guidelines for the modeling of multicast communications in many core settings. To this end, the scaling trends of aspects such as the multicast traffic intensity or the spatiotemporal injection distribution are analyzed. The novelty of this work resides both on its scalability-oriented approach and on the use of correlation metrics to evaluate potential prediction opportunities.
CitationAbadal, S., Mestres, A., Alarcon, E., Albert Cabellos-Aparicio, Martínez, R. Multicast on-Chip traffic analysis targeting manycore NoC design. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "2015 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2015): Turku, Finland: 4-6 March 2015". Turku: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 370-378.
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