Enviaments recents

  • Design and validation of a platform for electromagnetic fault injection 

    Balasch, Josep; Arumi Delgado, Daniel; Manich Bou, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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    Security is acknowledged as one of the main challenges in the design and deployment of embedded circuits. Devices need to operate on-the-field safely and correctly, even when at physical reach of potential adversaries. One ...
  • Crypto-test-lab for security validation of ECC co-processor test infrastructure 

    Lupón Roses, Emilio; Rodríguez Montañés, Rosa; Manich Bou, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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    Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. ...
  • Análisis del retardo en enlaces con protocolos ARQ y control de flujo: aplicación a una red estrella 

    Rubio Sola, Jose Antonio; Figueras Pàmies, Joan (Marcombo, 1983)
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    El objetivo de este trabajo se enmarca en el desarrollo de herramientas de cuantificación de los tiempos de retardo en redes de computadores. El análisis se ha centrado en la evaluación del tiempo medio de retardo en el ...
  • RRAM Based Random Bit Generation for Hardware Security Applications 

    Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Pehl, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end ...
  • Criteria for selecting a subset of indirect measurements for analog testing 

    Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (2016)
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    This work proposes a criterion to select a subset of indirect measurements avoiding redundant information. The key idea of the proposal is to reduce the actual number of measurements to be performed to those strictly ...
  • Improving indirect test efficiency using multi-directional tessellations in the measure space 

    Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Indirect test strategies have risen as a promising solution to overcome the challenges encountered in analog and mixed-signal circuit testing and the ever increasing device verification costs. This work explores the ...
  • RRAM based cell for hardware security applications 

    Arumi Delgado, Daniel; Manich Bou, Salvador; Rodríguez Montañés, Rosa (2016)
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    Resistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. ...
  • Backside polishing detector: a new protection against backside attacks 

    Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Mujal Colell, Jordi; Hernández García, David (2015)
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    Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this ...
  • Mixed-signal test band guarding using digitally coded indirect measurements 

    Gómez Pau, Álvaro; Balado Suárez, Luz María; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using ...
  • Power-aware voltage tuning for STT-MRAM reliability 

    Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Di Carlo, Stefano; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. ...
  • Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell 

    Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin- Transfer-Torque ...
  • STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations 

    Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. ...

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