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dc.contributor.authorAzevedo, Arnaldo
dc.contributor.authorMeenderinck, Cor
dc.contributor.authorJuurlink, Ben
dc.contributor.authorTerechko, Andrei
dc.contributor.authorHoogerbrugge, Jan
dc.contributor.authorÁlvarez Mesa, Mauricio
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-07-01T11:49:57Z
dc.date.available2010-07-01T11:49:57Z
dc.date.created2009-01-28
dc.date.issued2009-01-28
dc.identifier.citationAzevedo, A. [et al.]. Parallel H.264 decoding on an embedded multicore processor. A: International Conference on High Performance Embedded Architectures & Compilers (HiPEAC). "4th International Conference on High Performance and Embedded Architectures and Compilers". Paphos: Springer-Verlag, Berlin, Heidelberg,, 2009, p. 404-418.
dc.identifier.isbn978-3-540-92989-5
dc.identifier.urihttp://hdl.handle.net/2117/7957
dc.description.abstractIn previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial range. The previous results, however, investigate application scalability on an idealized multiprocessor. This work presents an implementation of the 3D-Wave strategy on a multicore architecture composed of NXP TriMedia TM3270 embedded processors. The results show that the parallel H.264 implementation scales very well, achieving a speedup of more than 54 on a 64-core processor. Potential drawbacks of the 3D-Wave strategy are that the memory requirements increase since there can be many frames in flight, and that the latencies of some frames might increase. To address these drawbacks, policies to reduce the number of frames in flight and the frame latency are also presented. The results show that our policies combat memory and latency issues with a negligible effect on the performance scalability.
dc.format.extent15 p.
dc.language.isoeng
dc.publisherSpringer-Verlag, Berlin, Heidelberg,
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshH.264
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshComputer networks -- Scalability
dc.titleParallel H.264 decoding on an embedded multicore processor
dc.typeConference report
dc.subject.lemacVídeo -- Compressió
dc.subject.lemacProcessament en paral·lel (Ordinadors) -- Arquitectura
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1007/978-3-540-92990-1_29
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac2574295
dc.description.versionPostprint (published version)
local.citation.authorAzevedo, A.; Meenderinck, C.; Juurlink, B.; Terechko, A.; Hoogerbrugge, J.; Alvarez, M.; Ramirez, A.
local.citation.contributorInternational Conference on High Performance Embedded Architectures & Compilers (HiPEAC)
local.citation.pubplacePaphos
local.citation.publicationName4th International Conference on High Performance and Embedded Architectures and Compilers
local.citation.startingPage404
local.citation.endingPage418


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