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dc.contributor.authorMadriles Gimeno, Carles
dc.contributor.authorLópez Muñoz, Pedro
dc.contributor.authorCodina Viñas, Josep M.
dc.contributor.authorGibert Codina, Enric
dc.contributor.authorLatorre Salinas, Fernando
dc.contributor.authorMartínez Vicente, Alejandro
dc.contributor.authorMartinez Morais, Raul
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-06-30T13:23:47Z
dc.date.available2010-06-30T13:23:47Z
dc.date.created2009-06
dc.date.issued2009-06
dc.identifier.citationMadriles, C. [et al.]. Boosting single-thread performance in multi-core systems through fine-grain multi-threading. A: International Symposium on Computer Architecture. "International Symposium on Computer Architecture". Austin, TX: ACM Press. Association for Computing Machinery, 2009, p. 474-483.
dc.identifier.isbn978-1-60558-526-0
dc.identifier.urihttp://hdl.handle.net/2117/7925
dc.description.abstractIndustry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism (TLP), and even a small part with limited TLP impose important constraints to the global performance, as explained by Amdahl’s law. In this paper we propose a novel approach for leveraging multiple cores to improve single-thread performance in a multi-core design. The proposed technique features a set of novel hardware mechanisms that support the execution of threads generated at compile time. These threads result from a fine-grain speculative decomposition of the original application and they are executed under a modified multi-core system that includes: (1) mechanisms to support multiple versions; (2) mechanisms to detect violations among threads; (3) mechanisms to reconstruct the original sequential order; and (4) mechanisms to checkpoint the architectural state and recovery to handle misspeculations. The proposed scheme outperforms previous hardware-only schemes to implement the idea of combining cores for executing single-thread applications in a multi-core design by more than 10% on average on Spec2006 for all configurations. Moreover, single-thread performance is improved by 41% on average when the proposed scheme is used on a Tiny Core, and up to 2.6x for some selected applications.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherACM Press. Association for Computing Machinery
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.titleBoosting single-thread performance in multi-core systems through fine-grain multi-threading
dc.typeConference report
dc.subject.lemacProcessadors en paral·lel -- Disseny
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1145/1555754.1555813
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
drac.iddocument2569588
dc.description.versionPostprint (published version)
upcommons.citation.authorMadriles, C.; López, P.; Codina, J.M.; Gibert, E.; Latorre, F.; Martinez, A.; Martinez, R.; González, A.
upcommons.citation.contributorInternational Symposium on Computer Architecture
upcommons.citation.pubplaceAustin, TX
upcommons.citation.publishedtrue
upcommons.citation.publicationNameInternational Symposium on Computer Architecture
upcommons.citation.startingPage474
upcommons.citation.endingPage483


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