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dc.contributor.authorErgin, Oguz
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorVera Rivera, Francisco Javier
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-06-29T10:22:01Z
dc.date.available2010-06-29T10:22:01Z
dc.date.created2009-09
dc.date.issued2009-09
dc.identifier.citationErgin, O. [et al.]. Reducing soft errors through operand width aware policies. "IEEE transactions on dependable and secure computing", Setembre 2009, vol. 6, núm. 3, p. 217-230.
dc.identifier.issn1545-5971
dc.identifier.urihttp://hdl.handle.net/2117/7881
dc.description.abstractSoft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper, we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. As a faster but less fault tolerant alternative to ECC and parity, we offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of different data-holding components of a processor. On average, techniques that make use of the narrowness of the values can provide 49 percent error detection, 45 percent error correction, or 27 percent error avoidance coverage for single bit upsets in the first level data cache across all Spec2K. In other structures such as the immediate field of the issue queue, an average error detection rate of 64 percent is achieved.
dc.format.extent14 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Programació
dc.subject.lcshSoftware failures
dc.titleReducing soft errors through operand width aware policies
dc.typeArticle
dc.subject.lemacProgramari -- Fiabilitat
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument2568878
dc.description.versionPostprint (published version)
upcommons.citation.authorErgin, O.; Unsal, O.; Vera, F.; González, A.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on dependable and secure computing
upcommons.citation.volume6
upcommons.citation.number3
upcommons.citation.startingPage217
upcommons.citation.endingPage230


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